/ Published in: VHDL
entity + architecture + simulation
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entity ffd is port(D, CLK, RST: in BIT; Q: out BIT); end; architecture BEH of ffd is begin process(CLK, RST) begin if RST = '1' then Q<='0'; elsif CLK='1' and CLK'EVENT then --flanco ascendente Q<=D; end if; end process; end; entity SIMUL is end; architecture SIM of SIMUL is signal D_aux, reset, Q_aux:bit; signal clock : bit:='0'; component ffd is port(D, CLK, RST: in BIT; Q: out BIT); end component; begin L1: ffd port map(D_aux,clock,reset,Q_aux); D_aux<= '0', '1' after 40 ns, '0' after 80 ns; --el tiempo es absoluto clock<= not clock after 20 ns; reset<= '1', '0' after 50 ns; end;