Posted By

yuconner on 08/10/06


Tagged

digital logic


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Fulladder 1bit


 / Published in: VHDL
 

Fulladder 1bit --Cin, Cout: Carry in, out

  1. entity full_adder is
  2. port(A, B, Cin : in bit; salida, Cout : out bit);
  3. end;
  4.  
  5. architecture beh of full_adder is
  6. begin
  7. process (A, B, Cin)
  8.  
  9. begin
  10. salida <= A xor B xor Cin ;
  11. Cout <= (A and B) or (A and Cin) or (B and Cin);
  12. end process;
  13. end;

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