Posted By

woofeR on 01/16/10


Tagged

display hex design digital segment seven verilog fpga spartan


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Hexadecimal to Seven Segment Display


 / Published in: VHDL
 

  1. module SevenSegment(ssOut, nIn);
  2. output reg [6:0] ssOut;
  3. input [3:0] nIn;
  4.  
  5. // ssOut format {g, f, e, d, c, b, a}
  6.  
  7. always @(nIn)
  8. case (nIn)
  9. 4'h0: ssOut = 7'b0111111;
  10. 4'h1: ssOut = 7'b0000110;
  11. 4'h2: ssOut = 7'b1011011;
  12. 4'h3: ssOut = 7'b1001111;
  13. 4'h4: ssOut = 7'b1100110;
  14. 4'h5: ssOut = 7'b1101101;
  15. 4'h6: ssOut = 7'b1111101;
  16. 4'h7: ssOut = 7'b0000111;
  17. 4'h8: ssOut = 7'b1111111;
  18. 4'h9: ssOut = 7'b1100111;
  19. 4'hA: ssOut = 7'b1110111;
  20. 4'hB: ssOut = 7'b1111100;
  21. 4'hC: ssOut = 7'b0111001;
  22. 4'hD: ssOut = 7'b1011110;
  23. 4'hE: ssOut = 7'b1111001;
  24. 4'hF: ssOut = 7'b1110001;
  25. endcase
  26. endmodule

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