Posted By

yuconner on 08/10/06


Tagged

digital


Versions (?)

Flip Flop D (FFD)


 / Published in: VHDL
 

entity + architecture + simulation

  1. entity ffd is
  2. port(D, CLK, RST: in BIT; Q: out BIT);
  3. end;
  4.  
  5. architecture BEH of ffd is
  6. begin
  7. process(CLK, RST)
  8. begin
  9. if RST = '1' then
  10. Q<='0';
  11. elsif CLK='1' and CLK'EVENT then --flanco ascendente
  12. Q<=D;
  13. end if;
  14. end process;
  15. end;
  16.  
  17.  
  18. entity SIMUL is
  19. end;
  20.  
  21. architecture SIM of SIMUL is
  22. signal D_aux, reset, Q_aux:bit;
  23. signal clock : bit:='0';
  24. component ffd is
  25. port(D, CLK, RST: in BIT; Q: out BIT);
  26. end component;
  27. begin
  28. L1: ffd port map(D_aux,clock,reset,Q_aux);
  29. D_aux<= '0', '1' after 40 ns, '0' after 80 ns; --el tiempo es absoluto
  30. clock<= not clock after 20 ns;
  31. reset<= '1', '0' after 50 ns;
  32. end;

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