Posted By

Feb30th1712 on 05/10/08


Tagged


Versions (?)

SHR SIPO Register


 / Published in: VHDL
 

Shift-right, serial-in-parallel-out register, using http://snipplr.com/view/6173/clock-divider/.

  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3.  
  4. entity SHRSIPO is
  5. port(
  6. di : in std_logic;
  7. clk : in std_logic;
  8. clrn : in std_logic;
  9. prn : in std_logic;
  10. out0 : out std_logic;
  11. out1 : out std_logic;
  12. out2 : out std_logic;
  13. out3 : out std_logic
  14. );
  15. end SHRSIPO;
  16.  
  17. architecture main of SHRSIPO is
  18. signal s : std_logic_vector(3 downto 1);
  19. signal clkout : std_logic;
  20.  
  21. component divider160m
  22. port(
  23. clk : in std_logic;
  24. clkout : out std_logic
  25. );
  26. end component;
  27.  
  28. component dff
  29. port(
  30. d : in std_logic;
  31. clk : in std_logic;
  32. clrn : in std_logic;
  33. prn : in std_logic;
  34. q : out std_logic
  35. );
  36. end component;
  37. begin
  38. w0: divider160m port map(clk, clkout);
  39.  
  40. w1: dff port map( di, clkout, clrn, prn, s(3) );
  41. w2: dff port map( s(3), clkout, clrn, prn, s(2) );
  42. w3: dff port map( s(2), clkout, clrn, prn, s(1) );
  43. w4: dff port map( s(1), clkout, clrn, prn, out0 );
  44.  
  45. out3 <= s(3);
  46. out2 <= s(2);
  47. out1 <= s(1);
  48. end main;

Report this snippet  

You need to login to post a comment.