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Feb30th1712 on 05/10/08


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Clock divider


 / Published in: VHDL
 

Slow the clock to 1 dHz.

  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.std_logic_unsigned.all;
  4.  
  5. entity divider160m is
  6. port(
  7. clk : in std_logic;
  8. clkout : out std_logic
  9. );
  10. end divider160m;
  11.  
  12. architecture main of divider160m is
  13. signal cnt: std_logic_vector(27 downto 0);
  14. begin
  15. process(clk)
  16. begin
  17. if(clk'event and clk = '1') then
  18. if cnt = 159999999 then
  19. cnt <= (others => '0');
  20. else
  21. cnt <= cnt + 1;
  22. end if;
  23. end if;
  24. clkout <= cnt(27);
  25. end process;
  26. end main;

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Posted By: Sadiq_meman on May 10, 2008

Posted By: Sadiq_meman on May 10, 2008

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