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Feb30th1712 on 05/10/08

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Clock divider

Published in: VHDL

Slow the clock to 1 dHz.

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity divider160m is
	port(
		clk	: in std_logic;
		clkout	: out std_logic
	);
end divider160m;
 
architecture main of divider160m is
	signal cnt: std_logic_vector(27 downto 0);
begin
	process(clk)
	begin
		if(clk'event and clk = '1') then
			if cnt = 159999999 then
				cnt <= (others => '0');
			else
				cnt <= cnt + 1;
			end if;
		end if;
		clkout <= cnt(27);
	end process;
end main;

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Posted By: Sadiq_meman on May 10, 2008
Posted By: Sadiq_meman on May 10, 2008

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