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Feb30th1712 on 05/10/08


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Load register


 / Published in: VHDL
 

3-bit register with load control, using http://snipplr.com/view/6171/21-mux/.

  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3.  
  4. entity loadRegister is
  5. port(
  6. q : in std_logic_vector(2 downto 0);
  7. load : in std_logic;
  8. clk : in std_logic;
  9. y : out std_logic_vector(2 downto 0);
  10. clrn : in std_logic;
  11. prn : in std_logic
  12. );
  13. end loadRegister;
  14.  
  15. architecture main of loadRegister is
  16. signal m, q: std_logic_vector(2 downto 0);
  17.  
  18. component mux
  19. port(
  20. a: in std_logic;
  21. b: in std_logic;
  22. s: in std_logic;
  23. z: out std_logic
  24. );
  25. end component;
  26.  
  27. component dff
  28. port(
  29. d : in std_logic;
  30. clk : in std_logic;
  31. clrn : in std_logic;
  32. prn : in std_logic;
  33. q : out std_logic
  34. );
  35. end component;
  36. begin
  37. w1: mux port map( q(0), i(0), load, m(0) );
  38. w2: mux port map( q(1), i(1), load, m(1) );
  39. w3: mux port map( q(2), i(2), load, m(2) );
  40.  
  41. w5: dff port map( m(0), clk, clrn, prn, q(0) );
  42. w6: dff port map( m(1), clk, clrn, prn, q(1) );
  43. w7: dff port map( m(2), clk, clrn, prn, q(2) );
  44.  
  45. y(0) <= q(0);
  46. y(1) <= q(1);
  47. y(2) <= q(2);
  48. end main;

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