/ Published in: VHDL
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module DualSevenSegment(O, AN, I1, I2, CLK); output [6:0] O ; output [3:0] AN; input [6:0] I1, I2; input CLK; reg bool; reg [15:0] count; reg [6:0] O ; reg [3:0] AN; initial begin bool = 0; count = 0; end always @(posedge CLK) begin count = count + 1; if (count == 0) begin case(bool) 0: begin AN = 4'b1110; O = I1; end 1: begin AN = 4'b1101; O = I2; end endcase bool = ~bool; end end endmodule
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thanks! I need it.