Posted By

woofeR on 01/16/10


Tagged

display hex design digital segment seven verilog fpga spartan dual


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Dual Seven Segment Display


 / Published in: VHDL
 

  1. module DualSevenSegment(O, AN, I1, I2, CLK);
  2. output [6:0] O ;
  3. output [3:0] AN;
  4. input [6:0] I1, I2;
  5. input CLK;
  6.  
  7. reg bool;
  8. reg [15:0] count;
  9. reg [6:0] O ;
  10. reg [3:0] AN;
  11.  
  12. initial
  13. begin
  14. bool = 0;
  15. count = 0;
  16. end
  17.  
  18. always @(posedge CLK)
  19. begin
  20. count = count + 1;
  21. if (count == 0)
  22. begin
  23. case(bool)
  24. 0: begin
  25. AN = 4'b1110;
  26. O = I1;
  27. end
  28. 1: begin
  29. AN = 4'b1101;
  30. O = I2;
  31. end
  32. endcase
  33. bool = ~bool;
  34. end
  35. end
  36.  
  37.  
  38. endmodule

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Posted By: kakaix on January 26, 2012

thanks! I need it.

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