Posted By

woofeR on 01/16/10


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controller design digital room verilog intelligent


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Intelligent Room Controller


 / Published in: VHDL
 

  1. module Lab8( CLK, PDout, PDin, Reset, ssO, AN, AC
  2. );
  3. input PDout, PDin;
  4. input CLK, Reset;
  5. output [6:0]ssO;
  6. output [3:0] AN;
  7. output AC;
  8. wire [1:0] w1;
  9. reg [3:0] w4, w5;
  10. wire [4:0] w3;
  11. wire [6:0] w6, w7, w8;
  12.  
  13. //reg [4:0] w12;
  14.  
  15. //initial begin
  16. //w12 = 5'b01010;
  17. //end
  18.  
  19. Steytir cokMuhimModul(CLK, PDout, PDin, Reset, w1);
  20. Counter CNTR(w1, AC, w3, CLK, Reset);
  21.  
  22. //w3 is OutToSS in Counter module
  23. always @(w3)
  24. begin
  25. w4 = {w3[3],w3[2],w3[1],w3[0]};
  26. w5 = {3'b000, w3[4]};
  27. end
  28.  
  29. SevenSegment S1(w6, w4);
  30. SevenSegment S2(w7, w5);
  31.  
  32. DualSevenSegment DualSS(w8, AN, w6, w7, CLK);
  33.  
  34. assign ssO = ~w8;
  35. endmodule
  36.  
  37. module Counter(IncDec, AC, OutToSS, Clk, Reset
  38. );
  39.  
  40. input Clk, Reset;
  41. input [1:0] IncDec;
  42. output [4:0] OutToSS;
  43. output AC;
  44. reg AC;
  45. reg [4:0] OutToSS;
  46.  
  47.  
  48. always @(posedge Clk)
  49. begin
  50.  
  51. //reset function
  52. if (Reset)
  53. begin
  54. OutToSS <= 5'b00000;
  55. end
  56. //when increment signal is 1, increment OutToSS by 1
  57. else if (!IncDec[0] && IncDec[1]) OutToSS <= OutToSS + 1;
  58. //when decrement signal is 1, decrement OutToSS by 1
  59. else if (IncDec[0] && !IncDec[1] && OutToSS!=0) OutToSS <= OutToSS - 1;
  60. else OutToSS <= OutToSS;
  61. end
  62.  
  63. //air conditioning
  64. //open air condition when OutToSS is 01000
  65. //close it when OutToSS is 00111 and 00000
  66. always @ (OutToSS or Reset)
  67. begin
  68. if(OutToSS == 5'b00111) AC <= 1'b0;
  69. else if(OutToSS == 5'b01000) AC <= 1'b1;
  70. else if(OutToSS == 5'b00000) AC <= 1'b0;
  71. end
  72.  
  73. endmodule
  74.  
  75. module Steytir(CLK, PDout, PDin, Reset, IncDec
  76. );
  77.  
  78. input CLK, PDout, PDin, Reset;
  79. output [1:0] IncDec;
  80.  
  81. reg [2:0] state, next_state;
  82. parameter A=3'b000, B=3'b001, C=3'b010, D=3'b011, E=3'b100, F=3'b101, G=3'b110, H=3'b111;
  83. reg [1:0]IncDec;
  84.  
  85. //reset function
  86. always @(posedge CLK)
  87. begin
  88. if(Reset)
  89. begin
  90. state <= A;
  91. end
  92. else
  93. begin
  94. state <= next_state;
  95. end
  96. end
  97.  
  98. //state machine implementation
  99. /*always @(PDout or PDin or state)
  100. begin
  101. case (state)
  102. A: if ((PDin == 1) && (PDout == 0))
  103. next_state <= B;
  104. else if ((PDin == 0) && (PDout == 1))
  105. next_state <= E;
  106. else if ((PDin == 1) && (PDout == 1))
  107. next_state <= A;
  108.  
  109. B: if ((PDin == 0) && (PDout == 1))
  110. next_state <= B;
  111. else if ((PDin == 0) && (PDout == 0))
  112. next_state <= C;
  113.  
  114. C: if ((PDin == 0) && (PDout == 0))
  115. next_state <= C;
  116. else if ((PDin == 0) && (PDout == 1))
  117. next_state <= D;
  118.  
  119. D: if ((PDin == 0) && (PDout == 1))
  120. next_state <= D;
  121. else if ((PDin == 1) && (PDout == 1))
  122. next_state <= A;
  123.  
  124. E: if ((PDin == 0) && (PDout == 1))
  125. next_state <= E;
  126. else if ((PDin == 0) && (PDout == 0))
  127. next_state <= F;
  128.  
  129. F: if ((PDin == 0) && (PDout == 0))
  130. next_state <= F;
  131. else if ((PDin == 1) && (PDout == 0))
  132. next_state <= G;
  133.  
  134. G: if ((PDin == 1) && (PDout == 0))
  135. next_state <= G;
  136. else if ((PDin == 1) && (PDout == 1))
  137. next_state <= A;
  138. endcase
  139. end
  140.  
  141. //output function
  142. always @ (PDout or PDin or state)
  143. begin
  144. case(state)
  145. A: begin Inc <= 0; Dec <=0; end
  146. B: begin Inc <= 0; Dec <=0; end
  147. C: begin Inc <= 0; Dec <=0; end
  148. //d'den gelince increment olcak
  149. D: if((PDin == 1) && (PDout ==1))
  150. begin
  151. Inc <= 1; //bura 1di hehe
  152. Dec <=0;
  153. end
  154. else
  155. begin
  156. Inc <= 0;
  157. Dec <= 0;
  158. end
  159. E: begin Inc <= 0; Dec <=0; end
  160. F: begin Inc <= 0; Dec <=0; end
  161. //g'den gelince decrement olcak
  162. G: if((PDin == 1) && (PDout ==1))
  163. begin
  164. Inc <= 0;
  165. Dec <= 1;
  166. end
  167. else
  168. begin
  169. Inc <= 0;
  170. Dec <= 0;
  171. end
  172. endcase
  173. */
  174.  
  175. //state function
  176. always @(PDin or PDout or state)
  177. begin
  178. case(state)
  179. A : begin
  180. if(PDin && PDout) next_state <= B;
  181. else next_state <= A;
  182. end
  183. B : begin
  184. if(PDout && PDin) next_state <= B;
  185. else if(PDout && ~PDin) next_state <= D;
  186. else if(~PDout && PDin) next_state <= C;
  187. else next_state <= A;
  188. end
  189. C : begin
  190. if(PDout && PDin) next_state <= B;
  191. else if(PDout && ~PDin) next_state <= A;
  192. else if(~PDout && PDin) next_state <= C;
  193. else next_state <= E;
  194. end
  195. D : begin
  196. if(PDout && PDin) next_state <= B;
  197. else if(PDout && ~PDin) next_state <= D;
  198. else if(~PDout && PDin) next_state <= D;
  199. else next_state <= F;
  200. end
  201. E : begin
  202. if(PDout && PDin) next_state<=B;
  203. else if(PDout && ~PDin) next_state <= G;
  204. else if(~PDout && PDin) next_state <= C;
  205. else next_state <= E;
  206. end
  207. F : begin
  208. if(PDout && PDin) next_state <= B;
  209. else if(PDout && ~PDin) next_state <= D;
  210. else if(~PDout && PDin) next_state <= H;
  211. else next_state <= F;
  212. end
  213. G : begin
  214. if(PDout && PDin) next_state <= B;
  215. else if(PDout && ~PDin) next_state <= G;
  216. else if(~PDout && PDin) next_state <= C;
  217. else next_state <= E;
  218. end
  219. H : begin
  220. if(PDout && PDin) next_state<=B;
  221. else if(PDout && ~PDin) next_state<=D;
  222. else if(~PDout && PDin) next_state<=H;
  223. else next_state <= F;
  224. end
  225. endcase
  226. end
  227.  
  228. //output function
  229. always@(PDout or PDin or IncDec or next_state or state)
  230. begin
  231. if((state == G) && PDout && PDin) IncDec<= 2'b10;
  232. else if((state == H) && PDout && PDin) IncDec<= 2'b01;
  233. else IncDec <= 2'b00;
  234. end
  235.  
  236.  
  237. endmodule

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