Snipplr - Feb30th1712 http://snipplr.com/users/Feb30th1712/language/vhdl Recent snippets posted on Snipplr.com en-us Sat, 11 Oct 2008 12:17:23 GMT (VHDL) SHR SIPO Register http://snipplr.com/view/6174/shr-sipo-register/ Shift-right, serial-in-parallel-out register, using http://snipplr.com/view/6173/clock-divider/.

]]> Sat, 10 May 2008 03:53:53 GMT http://snipplr.com/view/6174/shr-sipo-register/ (VHDL) Clock divider http://snipplr.com/view/6173/clock-divider/ Slow the clock to 1 dHz.

]]> Sat, 10 May 2008 03:49:32 GMT http://snipplr.com/view/6173/clock-divider/ (VHDL) Load register http://snipplr.com/view/6172/load-register/ 3-bit register with load control, using http://snipplr.com/view/6171/21-mux/.

]]> Sat, 10 May 2008 03:42:27 GMT http://snipplr.com/view/6172/load-register/ (VHDL) 2×1 MUX http://snipplr.com/view/6171/21-mux/ Two-to-one multiplexer.

]]> Sat, 10 May 2008 03:40:36 GMT http://snipplr.com/view/6171/21-mux/