Snipplr http://snipplr.com/language/vhdl Recent snippets posted on Snipplr.com en-us Wed, 09 Jul 2008 04:39:22 GMT (VHDL) SHR SIPO Register - Feb30th1712 http://snipplr.com/view/6174/shr-sipo-register/ Shift-right, serial-in-parallel-out register, using http://snipplr.com/view/6173/clock-divider/.

]]> Sat, 10 May 2008 03:53:53 GMT http://snipplr.com/view/6174/shr-sipo-register/ (VHDL) Clock divider - Feb30th1712 http://snipplr.com/view/6173/clock-divider/ Slow the clock to 1 dHz.

]]> Sat, 10 May 2008 03:49:32 GMT http://snipplr.com/view/6173/clock-divider/ (VHDL) Load register - Feb30th1712 http://snipplr.com/view/6172/load-register/ 3-bit register with load control, using http://snipplr.com/view/6171/21-mux/.

]]> Sat, 10 May 2008 03:42:27 GMT http://snipplr.com/view/6172/load-register/ (VHDL) 2×1 MUX - Feb30th1712 http://snipplr.com/view/6171/21-mux/ Two-to-one multiplexer.

]]> Sat, 10 May 2008 03:40:36 GMT http://snipplr.com/view/6171/21-mux/ (VHDL) Flip Flop D (FFD) - yuconner http://snipplr.com/view/771/flip-flop-d-ffd/ entity + architecture + simulation

]]> Thu, 10 Aug 2006 17:05:43 GMT http://snipplr.com/view/771/flip-flop-d-ffd/ (VHDL) Fulladder 1bit - yuconner http://snipplr.com/view/770/fulladder-1bit/ Fulladder 1bit --Cin, Cout: Carry in, out

]]> Thu, 10 Aug 2006 16:59:10 GMT http://snipplr.com/view/770/fulladder-1bit/