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<description>Recent snippets posted on Snipplr.com</description>
<language>en-us</language>
<pubDate>Fri, 24 May 2013 06:31:13 GMT</pubDate>
<item>
<title>(VHDL) Dual Seven Segment Display - woofeR</title>
<link>http://snipplr.com/view/26561/dual-seven-segment-display/</link>
<description><![CDATA[ <p></p> ]]></description>
<pubDate>Sat, 16 Jan 2010 12:24:43 GMT</pubDate>
<guid>http://snipplr.com/view/26561/dual-seven-segment-display/</guid>
</item>
<item>
<title>(VHDL) Hexadecimal to Seven Segment Display - woofeR</title>
<link>http://snipplr.com/view/26560/hexadecimal-to-seven-segment-display/</link>
<description><![CDATA[ <p></p> ]]></description>
<pubDate>Sat, 16 Jan 2010 12:24:12 GMT</pubDate>
<guid>http://snipplr.com/view/26560/hexadecimal-to-seven-segment-display/</guid>
</item>
<item>
<title>(VHDL) Intelligent Room Controller - woofeR</title>
<link>http://snipplr.com/view/26559/intelligent-room-controller/</link>
<description><![CDATA[ <p></p> ]]></description>
<pubDate>Sat, 16 Jan 2010 12:22:30 GMT</pubDate>
<guid>http://snipplr.com/view/26559/intelligent-room-controller/</guid>
</item>
<item>
<title>(VHDL) Thunderbird Tail Lights - woofeR</title>
<link>http://snipplr.com/view/26558/thunderbird-tail-lights/</link>
<description><![CDATA[ <p></p> ]]></description>
<pubDate>Sat, 16 Jan 2010 12:15:58 GMT</pubDate>
<guid>http://snipplr.com/view/26558/thunderbird-tail-lights/</guid>
</item>
<item>
<title>(VHDL) SHR SIPO Register - Feb30th1712</title>
<link>http://snipplr.com/view/6174/shr-sipo-register/</link>
<description><![CDATA[ <p>Shift-right, serial-in-parallel-out register, using http://snipplr.com/view/6173/clock-divider/.</p> ]]></description>
<pubDate>Sat, 10 May 2008 03:53:53 GMT</pubDate>
<guid>http://snipplr.com/view/6174/shr-sipo-register/</guid>
</item>
<item>
<title>(VHDL) Clock divider - Feb30th1712</title>
<link>http://snipplr.com/view/6173/clock-divider/</link>
<description><![CDATA[ <p>Slow the clock to 1 dHz.</p> ]]></description>
<pubDate>Sat, 10 May 2008 03:49:32 GMT</pubDate>
<guid>http://snipplr.com/view/6173/clock-divider/</guid>
</item>
<item>
<title>(VHDL) Load register - Feb30th1712</title>
<link>http://snipplr.com/view/6172/load-register/</link>
<description><![CDATA[ <p>3-bit register with load control, using http://snipplr.com/view/6171/21-mux/.</p> ]]></description>
<pubDate>Sat, 10 May 2008 03:42:27 GMT</pubDate>
<guid>http://snipplr.com/view/6172/load-register/</guid>
</item>
<item>
<title>(VHDL) 2×1 MUX - Feb30th1712</title>
<link>http://snipplr.com/view/6171/21-mux/</link>
<description><![CDATA[ <p>Two-to-one multiplexer.</p> ]]></description>
<pubDate>Sat, 10 May 2008 03:40:36 GMT</pubDate>
<guid>http://snipplr.com/view/6171/21-mux/</guid>
</item>
<item>
<title>(VHDL) Flip Flop D (FFD) - yuconner</title>
<link>http://snipplr.com/view/771/flip-flop-d-ffd/</link>
<description><![CDATA[ <p>entity + architecture + simulation</p> ]]></description>
<pubDate>Thu, 10 Aug 2006 17:05:43 GMT</pubDate>
<guid>http://snipplr.com/view/771/flip-flop-d-ffd/</guid>
</item>
<item>
<title>(VHDL) Fulladder 1bit - yuconner</title>
<link>http://snipplr.com/view/770/fulladder-1bit/</link>
<description><![CDATA[ <p>Fulladder 1bit
--Cin, Cout: Carry in, out</p> ]]></description>
<pubDate>Thu, 10 Aug 2006 16:59:10 GMT</pubDate>
<guid>http://snipplr.com/view/770/fulladder-1bit/</guid>
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